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1. general description the pcu9656 is a ufm i 2 c-bus controlled 24-bit led driver optimized for voltage switch dimming and blinking 100 ma red/green/blue /amber (rgba) leds. each ledn output has its own 8-bit resolution (256 steps) fi xed frequency individual pwm controller that operates at 97 khz (typical) wit h a duty cycle that is adjustable from 0 % to 99.6 % to allow the led to be set to a specific brightness value. an additional 8-bit resolution (256 steps) group pwm controller has both a frequency of 190 hz and an adjustable frequency between 24 hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all leds with the same value. each ledn output can be off, on (no pwm co ntrol), set at its individual pwm controller value or at both individual and group pwm controller values. the pcu9656 operates with a supply voltage range of 2.3 v to 5.5 v and the 100 ma open-drain outputs allow voltages up to 40 v for the led supply. the pcu9656 is one of the first led contro ller devices in a new ultra fast-mode (ufm) family. ufm devices offer higher frequency (up to 5 mhz). the active low output enable input pin (oe ) blinks all the ledn outputs and can be used to externally pwm the outputs, which is useful when multiple devices need to be dimmed or blinked together without using software control. software programmable led group and three sub call i 2 c-bus addresses allow all or defined groups of pcu9656 devices to respond to a common i 2 c-bus address, allowing for example, all red leds to be turned on or off at the same time or marquee chasing effect, thus minimizing i 2 c-bus commands. six hardware address pins allow up to 64 devices on the same bus. the software reset (swrst) call allows the master to perform a reset of the pcu9656 through the i 2 c-bus, identical to the power-on reset (por) that initializes the registers to their default state causing the output nand fe ts to be off (led off). this allows an easy and quick way to reconfigure all device registers to the same condition. a new feature to control ledn output pattern is incorporated in the pcu9656. a new control byte called ?chase byte ? allows enabling or disabling of selective ledn outputs depending on the value of the chase byte. th is feature greatly reduces the number of bytes to be sent to the pcu9656 when repet itive patterns need to be displayed as in creating a marquee chasing effect. pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver rev. 1 ? 8 december 2011 product data sheet
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 2 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 2. features and benefits ? 24 led drivers. each output programmable at: ? off ? on ? programmable led brightness ? programmable group dimming/blinking mi xed with individual led brightness ? 5 mhz ultra fast-mode unidirectional i 2 c-bus interface ? 256-step (8-bit) linear programmable brightness per ledn output varying from fully off (default) to maximum brightne ss using a 97 khz pwm signal ? 256-step group brightness control allows general dimming (using a 190 hz pwm signal) from fully off to maximum brightness (default) ? 256-step group blinking with frequency programmable from 24 hz to 10.73 s and duty cycle from 0 % to 99.6 % ? 24 open-drain outputs can sink between 0 ma to 100 ma and are tolerant to a maximum off state voltage of 40 v. no input function. ? output state change programmable on the ack nowledge (bit 9, this bit is always set to 1 by master) or the stop command to up date outputs byte-by-byte or all at the same time (default to ?change on stop?). ? active low output enable (oe ) input pin allows for hardwa re blinking and dimming of the leds ? six hardware address pins allow 64 pcu9656 devices to be connected to the same ufm i 2 c-bus and to be individually programmed ? four software programmable ufm i 2 c-bus addresses (one led group call address and three led sub call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for ?all call? so that all the pcu9656s on the i 2 c-bus can be addressed at the same time and the second register used for three different addresses so that 1 3 of all devices on the bus can be addressed at the same time in a group). software enable and disable for i 2 c-bus address. ? a chase byte allows execution of predefin ed on/off pattern for the 24 ledn outputs ? software reset feature (s wrst call) allows the devic e to be reset through the ufm i 2 c-bus ? 25 mhz internal oscillator requ ires no external components ? internal power-on reset ? noise filter on usda/uscl inputs ? glitch-free ledn outputs on power-up ? supports hot insertion ? low standby current ? operating power supply voltage (v dd ) range of 2.3 v to 5.5 v ? 5.5 v tolerant inputs on non-led pins ? ? 40 ? c to +85 ? c operation ? esd protection exceeds 2000 v hbm per jesd22-a114, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? package offered: lqfp48
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 3 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 3. applications ? rgb or rgba led drivers ? led status information ? led displays ? lcd backlights ? keypad backlights for cellular phones or handheld devices 4. ordering information 5. block diagram table 1. ordering information type number topside mark package name description version PCU9656B pcu9656 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 fig 1. block diagram of pcu9656 a0 a1 a2 a3 a4 002aag246 ufm i 2 c-bus control input filter pcu9656 power-on reset uscl usda v dd v ss led state select register pwm register x brightness control grpfreq register grppwm register mux/ control '0' C permanently off '1' C permanently on led0 fet driver led1 led23 24.3 khz 25 mhz oscillator 97 khz 190 hz a5 oe
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 4 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for lqfp48 a2 a3 a4 v ss led8 led9 led10 led11 v ss a5 n.c. oe v ss led12 led13 led14 led15 v ss v ss led16 led17 led18 led19 v ss led7 v ss led6 led5 led4 v ss v ss led3 led2 led1 led0 v ss v ss a1 a0 v ss led23 led22 led21 led20 v dd usda uscl v ss PCU9656B 002aag247 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 table 2. pin description symbol pin type description v ss 1, 6, 7, 12, 16, 21, 25, 30, 31, 36, 37, 45, 48 power supply supply ground led0 2 o led driver 0 led1 3 o led driver 1 led2 4 o led driver 2 led3 5 o led driver 3 led4 8 o led driver 4 led5 9 o led driver 5 led6 10 o led driver 6 led7 11 o led driver 7 a2 13 i address input 2 a3 14 i address input 3 a4 15 i address input 4 led8 17 o led driver 8 led9 18 o led driver 9 led10 19 o led driver 10
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 5 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver led11 20 o led driver 11 a5 22 i address input 5 n.c. 23 i do not connect; reserved input oe 24 i active low output enable for leds led12 26 o led driver 12 led13 27 o led driver 13 led14 28 o led driver 14 led15 29 o led driver 15 led16 32 o led driver 16 led17 33 o led driver 17 led18 34 o led driver 18 led19 35 o led driver 19 uscl 38 i ufm serial clock line usda 39 i ufm serial data line v dd 40 power supply supply voltage led20 41 o led driver 20 led21 42 o led driver 21 led22 43 o led driver 22 led23 44 o led driver 23 a0 46 i address input 0 a1 47 i address input 1 table 2. pin description ?continued symbol pin type description
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 6 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7. functional description refer to figure 1 ? block diagram of pcu9656 ? . 7.1 device addresses following a start condition, the bus master must output the address of the slave it is accessing. there are a maximum of 64 possible programmable addresses using the six hardware address pins. one of these addresses cannot be used as it is reserved for software reset (swrst), leaving a maximum of 63 addre sses. using other reserved addresses can reduce the total number of possible addresses even further. 7.1.1 regular ufm i 2 c-bus slave address the ufm i 2 c-bus slave address of the pcu9656 is shown in figure 3 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low externally. remark: using reserved i 2 c-bus addresses will interfere wit h other devices, but only if the devices are on the bus and/or the bus will be open to other i 2 c-bus systems at some later date. in a closed system where the designer controls the address assignment these addresses can be used since the pcu9656 treats them like any other address. the led all call and software reset and pca9564 or pca9665 slave address (if on the bus) can never be used for individual device addresses. ? pcu9656 led all call address (1110 000) and software reset (0000 0110) which are active on start-up ? pca9564 (0000 000) or pca9665 (1110 000 ) slave address which is active on start-up ? ?reserved for future use? i 2 c-bus addresses (0000 011, 1111 1xx) ? slave devices that use the 10-bit addressing scheme (1111 0xx) ? slave devices that are designed to resp ond to the general call address (0000 000) ? high-speed mode (hs-mode) master code (0000 1xx) the last bit of the address byte defines the op eration to be performed. no read available with ufm. for ufm i 2 c-bus, there is only write operation in slave device. fig 3. slave address 0 002aag248 0 a5 a4 a3 a2 a1 a0 hardware selectable slave address w (write only)
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 7 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.1.2 led all call ufm i 2 c-bus address ? default power-up value (allcalladr register): e0h or 1110 000 ? programmable through i 2 c-bus (volatile programming) ? at power-up, led all call i 2 c-bus address is enabled see section 7.3.9 ? allcalladr, led all call ufm i 2 c-bus address ? for more detail. remark: the default led all call i 2 c-bus address (e0h or 1110 000) must not be used as a regular i 2 c-bus slave address since this address is enabled at power-up. all of the pcu9656s on the i 2 c-bus will respond to the ad dress if sent by the i 2 c-bus master. 7.1.3 led sub call ufm i 2 c-bus addresses ? 3 different ufm i 2 c-bus addresses can be used ? default power-up values: ? subadr1 register: e2h or 1110 001 ? subadr2 register: e4h or 1110 010 ? subadr3 register: e8h or 1110 100 ? programmable through ufm i 2 c-bus (volatile programming) ? at power-up, all sub call ufm i 2 c-bus addresses are disabled see section 7.3.8 ? subadr1 to subadr3, ufm i 2 c-bus subaddress 1 to 3 ? for more detail. 7.1.4 software reset ufm i 2 c-bus address the address shown in figure 4 is used when a reset of the pcu9656 needs to be performed by the master. the software reset address (swrst call) must be used with w =logic0. if w = logic 1, the pcu9656 does not recognize the swrst. see section 7.6 ? software reset ? for more detail. remark: the software reset ufm i 2 c-bus address is a reserved address and cannot be used as a regular ufm i 2 c-bus slave address or as an led all call or led sub call address. fig 4. software reset address 0 002aag249 0 0 0 0 0 1 1 w (write only)
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 8 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.2 control register following the slave address, led all call address or led sub call address, the bus master will send a byte to the pcu9656, wh ich will be stored in the control register. the lowest 6 bits are used as a pointer to determine which re gister will be accessed (d[5:0]). the highest bit is used as auto-increment flag (aif). this bit along with the mode1 register bit 5 an d bit 6 provide the auto-increment feature. bit 6 of the control register is not used. when the auto-increment flag is set (aif = logic 1), the six low order bits of the control register are automatically incremented after a write. this allows the user to program the registers sequentially. four different types of auto-increment are possible, depending on ai1 and ai0 values of mode1 register. [1] ai1 and ai0 come from mode1 register. remark: other combinations not shown in ta b l e 3 (aif + ai[1:0] = 001b, 010b and 011b) are reserved and must not be used for proper device operation. aif + ai[1:0] = 000b is used when the same register must be accessed several times during a single i 2 c-bus communication, for example, changes the brightness of a single led. data is overwritten each time the register is accessed during a write operation. aif + ai[1:0] = 100b is used when all the registers must be sequentially accessed, for example, power-up programming. reset state = 80h remark: the control register does not apply to the software reset ufm i 2 c-bus address. fig 5. control register table 3. auto-increment options aif ai1 [1] ai0 [1] function 0 0 0 no auto-increment 1 0 0 auto-increment for all registers. d[5:0] roll over to 0h after the last register 26h is accessed. 1 0 1 auto-increment for individual brightne ss registers only. d[5:0] roll over to 02h after the last register (19h) is accessed. 1 1 0 auto-increment for global control regi sters and chase register. d[5:0] roll over to 1ah after the last register (1ch) is accessed. 1 1 1 auto-increment for individual brightness registers; global control registers and chase register. d[5:0] roll over to 0 2h after the last register (1ch) is accessed. 002aag250 aif x d5 d4 d3 d2 d1 d0 auto-increment flag register address don't care (must be 0)
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 9 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver aif + ai[1:0] = 101b is used when the 24 led drivers must be individually programmed with different values during the same i 2 c-bus communication, for example, changing color setting to another color setting. aif + ai[1:0] = 110b is used when the led drivers must be globally programmed with different settings during the same i 2 c-bus communication, for example, global brightness or blinking change. aif + ai[1:0] = 111b is used when the 24 led drivers must be individually programmed with different values in addition to global programming. only the 6 least significant bits d[5:0] ar e affected by the aif, ai1 and ai0 bits. when the control register is written, the regi ster entry point determined by d[5:0] is the first register that will be addressed (write operation), and can be anywhere between 0h and 26h (as defined in ta b l e 4 ). when aif = 1, the auto-increment flag is set and the rollover value at which the register incr ement stops and goes to the next one is determined by aif, ai1 and ai2. see ta b l e 3 for rollover values. for example, if mode1 register bit ai1 = 0 and ai0 = 1 and if the cont rol register = 1010 0000, then the register addressing sequence will be (in hex): 20 ? 21 ? ? ? 26 ? 0 ? 1 ? 2 ? ? ? 19 ? 02 ? 03 ? ? ? 19 ? 02 ? as long as the master keeps writing data. 7.3 register definitions table 4. register summary [1] [2] register number (hex) d5 d4 d3 d2 d1 d0 name type function 00 0 0 0 0 0 0 mode1 write only mode register 1 01 0 0 0 0 0 1 mode2 write only mode register 2 02 0 0 0 0 1 0 pwm0 write only brightness control led0 03 0 0 0 0 1 1 pwm1 write only brightness control led1 04 0 0 0 1 0 0 pwm2 write only brightness control led2 05 0 0 0 1 0 1 pwm3 write only brightness control led3 06 0 0 0 1 1 0 pwm4 write only brightness control led4 07 0 0 0 1 1 1 pwm5 write only brightness control led5 08 0 0 1 0 0 0 pwm6 write only brightness control led6 09 0 0 1 0 0 1 pwm7 write only brightness control led7 0a 0 0 1 0 1 0 pwm8 write only brightness control led8 0b 0 0 1 0 1 1 pwm9 write only brightness control led9 0c 0 0 1 1 0 0 pwm10 write only brightness control led10 0d 0 0 1 1 0 1 pwm11 write only brightness control led11 0e 0 0 1 1 1 0 pwm12 write only brightness control led12 0f 0 0 1 1 1 1 pwm13 write only brightness control led13 10 0 1 0 0 0 0 pwm14 write only brightness control led14 11 0 1 0 0 0 1 pwm15 write only brightness control led15 12 0 1 0 0 1 0 pwm16 write only brightness control led16 13 0 1 0 0 1 1 pwm17 write only brightness control led17
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 10 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver [1] only d[5:0] = 00 0000 to 10 0110 are allowed and will be recognized. d[5:0] = 10 0111 to 11 1111 are reserved and may not be recognized. [2] when writing to the control register, bit 6 should be programmed with logic 0 for proper device operation. 14 0 1 0 1 0 0 pwm18 write only brightness control led18 15 0 1 0 1 0 1 pwm19 write only brightness control led19 16 0 1 0 1 1 0 pwm20 write only brightness control led20 17 0 1 0 1 1 1 pwm21 write only brightness control led21 18 0 1 1 0 0 0 pwm22 write only brightness control led22 19 0 1 1 0 0 1 pwm23 write only brightness control led23 1a 0 1 1 0 1 0 grppwm write only g roup duty cycle control 1b 0 1 1 0 1 1 grpfreq write only group frequency 1c 0 1 1 1 0 0 chase write only chase control 1d 0 1 1 1 0 1 ledout0 write only ledn output state 0 1e 0 1 1 1 1 0 ledout1 write only ledn output state 1 1f 0 1 1 1 1 1 ledout2 write only ledn output state 2 20 1 0 0 0 0 0 ledout3 write only ledn output state 3 21 1 0 0 0 0 1 ledout4 write only ledn output state 4 22 1 0 0 0 1 0 ledout5 write only ledn output state 5 23 1 0 0 0 1 1 subadr1 write only i 2 c-bus subaddress 1 24 1 0 0 1 0 0 subadr2 write only i 2 c-bus subaddress 2 25 1 0 0 1 0 1 subadr3 write only i 2 c-bus subaddress 3 26 1 0 0 1 1 0 allcalladr write only led all call i 2 c-bus address table 4. register summary [1] [2] ?continued register number (hex) d5 d4 d3 d2 d1 d0 name type function
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 11 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.3.1 mode register 1, mode1 [1] it takes 500 ? s max. for the oscillator to be up and running once sleep bit has been set to logic 1. timings on ledn outputs are not guaranteed if pwmx, grppwm or grpfreq registers are accessed within the 500 ? s window. [2] no blinking or dimming is possi ble when the oscillator is off. 7.3.2 mode register 2, mode2 [1] change of the outputs at the stop command allows synchroniz ing outputs of more than one pcu9656. applicable to registers fro m 02h (pwm0) to 22h (ledout) only. table 5. mode1 - mode register 1 (address 00h) bit description legend: * default value. bit symbol access value description 7 aif not user programmable 0 register auto-increment disabled. 1* register auto-increment enabled (write default logic 1). 6 ai1 w 0* auto-increment bit 1 = 0. auto-increment range as defined in ta b l e 3 . 1 auto-increment bit 1 = 1. auto-increment range as defined in ta b l e 3 . 5 ai0 w 0* auto-increment bit 0 = 0. auto-increment range as defined in ta b l e 3 . 1 auto-increment bit 0 = 1. auto-increment range as defined in ta b l e 3 . 4 sleep w 0 normal mode [1] . 1* low power mode. oscillator off [2] . 3 sub1 w 0* pcu9656 does not respond to i 2 c-bus subaddress 1. 1 pcu9656 responds to i 2 c-bus subaddress 1. 2 sub2 w 0* pcu9656 does not respond to i 2 c-bus subaddress 2. 1 pcu9656 responds to i 2 c-bus subaddress 2. 1 sub3 w 0* pcu9656 does not respond to i 2 c-bus subaddress 3. 1 pcu9656 responds to i 2 c-bus subaddress 3. 0 allcall w 0 pcu9656 does not respond to led all call i 2 c-bus address. 1* pcu9656 responds to led all call i 2 c-bus address. table 6. mode2 - mode register 2 (address 01h) bit description legend: * default value. bit symbol access value description 7 - not user programmable 0* reserved, write must always be a logic 0 6 - not user programmable 0* reserved, write must always be a logic 0 5 dmblnk w 0* group control = dimming. 1 group control = blinking. 4 invrt w 0* reserved, write must always be a logic 0 3 och w 0* outputs change on stop command [1] 1 outputs change on ninth clock cycle (scl) 2 - w 1* reserved, write must always be a logic 1 1 - w 0* reserved, write must always be a logic 0 0 - w 1* reserved, write must always be a logic 1
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 12 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.3.3 pwm0 to pwm23, individual brightness control a typical 97 khz frequency signal is used for each output. duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = ledn output off) to ffh (99.6 % duty cycle = ledn output at maximum br ightness). applicable to ledn outputs programmed with ldrx = 10 or 11 (ledout0 to ledout5 registers). (1) table 7. pwm0 to pwm23 - pwm registers 0 to 23 (address 02h to 19h) bit description legend: * default value. address register bit symbol access value description 02h pwm0 7:0 idc0[7:0] w 0000 0000* pwm0 individual duty cycle 03h pwm1 7:0 idc1[7:0] w 0000 0000* pwm1 individual duty cycle 04h pwm2 7:0 idc2[7:0] w 0000 0000* pwm2 individual duty cycle 05h pwm3 7:0 idc3[7:0] w 0000 0000* pwm3 individual duty cycle 06h pwm4 7:0 idc4[7:0] w 0000 0000* pwm4 individual duty cycle 07h pwm5 7:0 idc5[7:0] w 0000 0000* pwm5 individual duty cycle 08h pwm6 7:0 idc6[7:0] w 0000 0000* pwm6 individual duty cycle 09h pwm7 7:0 idc7[7:0] w 0000 0000* pwm7 individual duty cycle 0ah pwm8 7:0 idc8[7:0] w 0000 0000* pwm8 individual duty cycle 0bh pwm9 7:0 idc9[7:0] w 0000 0000* pwm9 individual duty cycle 0ch pwm10 7:0 idc10[7:0] w 0000 0000* pwm10 individual duty cycle 0dh pwm11 7:0 idc11[7:0] w 0000 0000* pwm11 individual duty cycle 0eh pwm12 7:0 idc12[7:0] w 0000 0000* pwm12 individual duty cycle 0fh pwm13 7:0 idc13[7:0] w 0000 0000* pwm13 individual duty cycle 10h pwm14 7:0 idc14[7:0] w 0000 0000* pwm14 individual duty cycle 11h pwm15 7:0 idc15[7:0] w 0000 0000* pwm15 individual duty cycle 12h pwm16 7:0 idc16[7:0] w 0000 0000* pwm16 individual duty cycle 13h pwm17 7:0 idc17[7:0] w 0000 0000* pwm17 individual duty cycle 14h pwm18 7:0 idc18[7:0] w 0000 0000* pwm18 individual duty cycle 15h pwm19 7:0 idc19[7:0] w 0000 0000* pwm19 individual duty cycle 16h pwm20 7:0 idc20[7:0] w 0000 0000* pwm20 individual duty cycle 17h pwm21 7:0 idc21[7:0] w 0000 0000* pwm21 individual duty cycle 18h pwm22 7:0 idc22[7:0] w 0000 0000* pwm22 individual duty cycle 19h pwm23 7:0 idc23[7:0] w 0000 0000* pwm23 individual duty cycle duty cycle idcx 7 : 0 ?? 256 --------------------------- =
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 13 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.3.4 grppwm, group duty cycle control when dmblnk bit (mode2 register) is programmed with logic 0, a 190 hz typical frequency signal is superimposed with the 97 khz individual brightness control signal. grppwm is then used as a global brightness control allowing the ledn outputs to be dimmed with the same value. the value in grpfreq is then a ?don?t care?. general brightness for the 24 outputs is co ntrolled through 256 linear steps from 00h (0 % duty cycle = ledn output off) to ffh (9 9.6 % duty cycle = maximum brightness). applicable to ledn outputs programmed with ldrx = 11 (ledout0 to ledout5 registers). when dmblnk bit is programmed with logic 1, grppwm and grpfreq registers define a global blinking pattern, where grpfreq contains the blinking period (from 24 hz to 10.73 s) and grppwm the duty cycle (on/off ratio in %). (2) 7.3.5 grpfreq, group frequency grpfreq is used to program the global blinking period when dmblnk bit (mode2 register) is equal to 1. value in this re gister is a ?don?t care? when dmblnk = 0. applicable to ledn outputs programmed with ldrx = 11 (ledout0 to ledout5 registers). blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 hz) to ffh (10.73 s). (3) table 8. grppwm - group brightness control register (address 1ah) bit description legend: * default value address register bit symbol access value description 1ah grppwm 7:0 gdc[7:0] w 1111 1111* grppwm register duty cycle gdc 7 : 0 ?? 256 -------------------------- = table 9. grpfreq - group frequency regi ster (address 1bh) bit description legend: * default value. address register bit symbol access value description 1bh grpfreq 7:0 gfrq[7:0] w 0000 0000* grpfreq register global blinking period gfrq 7 : 0 ?? 1 + 24 --------------------------------------- - s ?? =
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 14 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.3.6 chase control chase is used to program the ledn output on/off pattern. the contents of the chase register is used to enable one of th e ledn output patterns, as indicated in table 11 . by repeated, sequential access to this table via the chase register, a chase pattern, e.g., marquee effect, can be easily programmed with minimal number of commands. once the chase register is accessed, the data bytes that follow will be used as an index value to pick the ledn output patterns defined by ta b l e 11 ? chase sequence ? . this register always updates on ninth clock cycle (uscl). it is used to gate the oe signal at each of the ledn pins such that: ? oe = 1: all leds are off ? oe = 0: those leds corresponding to the ?x?s in ta b l e 11 are on any write to this register takes effe ct at the ninth clock cycle (uscl). table 10. chase - chase pattern control register (address 1ch) bit description legend: * default value. address register bit symbol access value description 1ch chase 7:0 chc[7:0] w 0000 0000* chase register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 15 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver table 11. chase sequence x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 00xxxxxxxxxxxxxxxxxxxxxxxxall leds on 01 01 all leds off 02 02xxxxxxxxxxxx 1 2 chase b 03 03xxxxxxxxxxxx 1 2 chase a 0404xxxxxxxx 1 3 chase c 0505xxxxxxxx 1 3 chase b 0606xxxxxxxx 1 3 chase a 07 07 x ltr_0_on (1 ? left to right_start) 08 08 x ltr_1_on 09 09 x ltr_2_on 10 0a x ltr_3_on 11 0b x ltr_4_on 12 0c x ltr_5_on 13 0d x ltr_6_on 14 0e x ltr_7_on 15 0f x ltr_8_on 16 10 x ltr_9_on 17 11 x ltr_10_on 18 12 x ltr_11_on 19 13 x ltr_12_on 20 14 x ltr_13_on 21 15 x ltr_14_on 22 16 x ltr_15_on 23 17 x ltr_16_on 24 18 x ltr_17_on 25 19 x ltr_18_on 26 1a x ltr_19_on 27 1b x ltr_20_on
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 16 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 28 1c x ltr_21_on 29 1d x ltr_22_on 30 1e x ltr_23_on (1 ? left to right_end) 31 1f x x 2 ? left to right_start 32 20 x x 33 21 x x 34 22 x x 35 23 x x 36 24 x x 37 25 x x 38 26 x x 39 27 xx 40 28 xx 41 29 xx 42 2a xx2 ? left to right_end 43 2b x x x 3 ? left to right_start 44 2c x x x 45 2d x x x 46 2e x x x 47 2f x x x 48 30 xxx 49 31 xxx 50 32 xxx3 ? left to right_end 51 33 x x x x 4 ? left to right_start 52 34 x x x x 53 35 x x x x 54 36 x x x x 55 37 xxxx table 11. chase sequence ?continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 17 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 56 38 xxxx4 ? left to right_end 57 39 x x x x x 5 ? left to right_start 58 3a x x x x x 59 3b x x x x x 60 3c xxxxx 61 3d xxxx5 ? left to right_end 62 3e x x x x x x 6 ? left to right_start 63 3f xxxxxx 64 40 xxxxxx 65 41 xxxxxx6 ? left to right_end 66 42 x x1 ? implode_start 67 43 x x 68 44 x x 69 45 x x 70 46 x x 71 47 x x 72 48 x x 73 49 x x 74 4a x x 75 4b x x 76 4c x x 77 4d x x 1 ? implode_end 78 4e x x xx2 ? implode_start 79 4f x x xx 80 50 x x x x 81 51 x x x x 82 52 x x x x 83 53 x x x x 84 54 x x 2 ? implode_end table 11. chase sequence ?continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 18 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 85 55 x x x xxx3 ? implode_start 86 56 x x x x x x 87 57 xxx xxx 88 58 xxxxxx 89 59 x x x x 90 5a x x 3 ? implode_end 91 5b x x x x xxxx4 ? implode_start 92 5c x x x x x x x x 93 5d xxxxxxxx 94 5e x x x x 95 5f x x 4 ? implode_end 96 60 x left to right_wipe_start 97 61 x x 98 62 x x x 99 63 x x x x 100 64xxxxx 101 65xxxxxx 102 66xxxxxxx 103 67xxxxxxxx 104 68xxxxxxxxx 105 69xxxxxxxxxx 106 6axxxxxxxxxxx 107 6bxxxxxxxxxxxx 108 6cxxxxxxxxxxxxx 109 6dxxxxxxxxxxxxxx 110 6exxxxxxxxxxxxxxx 111 6fxxxxxxxxxxxxxxxx 112 70xxxxxxxxxxxxxxxxx 113 71xxxxxxxxxxxxxxxxxx table 11. chase sequence ?continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 19 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 114 72xxxxxxxxxxxxxxxxxxx 115 73xxxxxxxxxxxxxxxxxxxx 116 74xxxxxxxxxxxxxxxxxxxxx 117 75xxxxxxxxxxxxxxxxxxxxxx 118 76xxxxxxxxxxxxxxxxxxxxxxx 119 77xxxxxxxxxxxxxxxxxxxxxxxxleft to right_wipe_end 120 78 x right to left_wipe_start 121 79 xx 122 7a xxx 123 7b xxxx 124 7c xxxxx 125 7d xxxxxx 126 7e xxxxxxx 127 7f xxxxxxxx 128 80 xxxxxxxxx 129 81 xxxxxxxxxx 130 82 xxxxxxxxxxx 131 83 xxxxxxxxxxxx 132 84 xxxxxxxxxxxxx 133 85 xxxxxxxxxxxxxx 134 86 xxxxxxxxxxxxxxx 135 87 xxxxxxxxxxxxxxxx 136 88 xxxxxxxxxxxxxxxxx 137 89 xxxxxxxxxxxxxxxxxx 138 8a xxxxxxxxxxxxxxxxxxx 139 8b xxxxxxxxxxxxxxxxxxxx 140 8c xxxxxxxxxxxxxxxxxxxxx 141 8d xxxxxxxxxxxxxxxxxxxxxx table 11. chase sequence ?continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 20 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 142 8e xxxxxxxxxxxxxxxxxxxxxxx 143 8fxxxxxxxxxxxxxxxxxxxxxxxxright to left_wipe_end 144 90 all ledn outputs disabled for chase byte = 90h to ffh. reserved for future use. chase byte = ffh is used to exit the chase mode. table 11. chase sequence ?continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 21 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.3.7 ledout0 to ledout5, led driver output state ldrx = 00 ? led driver x is off (default power-up state). ldrx = 01 ? led driver x is fully on (individual brightness and group dimming/blinking not controlled). ldrx = 10 ? led driver x individual brightness can be controlled through its pwmx register. ldrx = 11 ? led driver x individual brightness and group dimming/blinking can be controlled through its pwmx register and the grppwm registers. table 12. ledout0 to ledout5 - led driver ou tput state register (address 1dh to 22h) bit description legend: * default value. address register bit symbol access value description 1dh ledout0 7:6 ldr3 w 00* led3 output state control 5:4 ldr2 w 00* led2 output state control 3:2 ldr1 w 00* led1 output state control 1:0 ldr0 w 00* led0 output state control 1eh ledout1 7:6 ldr7 w 00* led7 output state control 5:4 ldr6 w 00* led6 output state control 3:2 ldr5 w 00* led5 output state control 1:0 ldr4 w 00* led4 output state control 1fh ledout2 7:6 ldr11 w 00* led1 1 output state control 5:4 ldr10 w 00* led10 output state control 3:2 ldr9 w 00* led9 output state control 1:0 ldr8 w 00* led8 output state control 20h ledout3 7:6 ldr15 w 00* led1 5 output state control 5:4 ldr14 w 00* led14 output state control 3:2 ldr13 w 00* led13 output state control 1:0 ldr12 w 00* led12 output state control 21h ledout4 7:6 ldr19 w 00* led1 9 output state control 5:4 ldr18 w 00* led18 output state control 3:2 ldr17 w 00* led17 output state control 1:0 ldr16 w 00* led16 output state control 22h ledout5 7:6 ldr23 w 00* led2 3 output state control 5:4 ldr22 w 00* led22 output state control 3:2 ldr21 w 00* led21 output state control 1:0 ldr20 w 00* led20 output state control
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 22 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.3.8 subadr1 to subadr3, ufm i 2 c-bus subaddress 1 to 3 subaddresses are programmable through the ufm i 2 c-bus. default power-up values are e2h, e4h, e8h, and the device(s) will not reco gnize these addresses right after power-up (the corresponding subx bit in mode1 register is equal to 0). once subaddresses have been programmed to their right values, subx bits need to be set to logic 1 in order to have the device recognize these addresses (mode1 register). only the 7 msbs representing the i 2 c-bus subaddress are valid. the lsb in subadrx register is a reserved bit and must write logic 0. when subx is set to logic 1 in mode1 register, the corresponding i 2 c-bus subaddress can be used during a ufm i 2 c-bus write sequence. 7.3.9 allcalladr, led all call ufm i 2 c-bus address the led all call i 2 c-bus address allows all the pcu9656s on the bus to be programmed at the same time (allcall bit in register mode1 must be equal to logic 1 (power-up default state)). this address is programmable through the i 2 c-bus and can be used during a ufm i 2 c-bus write sequence. the register address can also be programmed as a sub call. only the 7 msbs representing the all call i 2 c-bus address are valid. the lsb in allcalladr register is a reserved bit and must write logic 0. if allcall bit = 0 in mode1 register, the device does not recognize the address programmed in register allcalladr. table 13. subadr1 to subadr3 - ufm i 2 c-bus subaddress registers 1 to 3 (address 23h to 25h) bit description legend: * default value. address register bit symbol access value description 23h subadr1 7:1 a1[7:1] w 1110 001* i 2 c-bus subaddress 1 0 a1[0] w only 0* reserved (must write logic 0) 24h subadr2 7:1 a2[7:1] w 1110 010* i 2 c-bus subaddress 2 0 a2[0] w only 0* reserved (must write logic 0) 25h subadr3 7:1 a3[7:1] w 1110 100* i 2 c-bus subaddress 3 0 a3[0] w only 0* reserved (must write logic 0) table 14. allcalladr - led all call ufm i 2 c-bus address register (address 26h) bit description legend: * default value. address register bit symbol access value description 26h allcalladr 7:1 ac[7:1] w 1110 000* allcall i 2 c-bus address register 0 ac[0] w only 0* reserved (must write logic 0)
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 23 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 7.4 active low out put enable input the active low output enable (oe ) pin, allows to enable or disable all the ledn outputs at the same time. ? when a low level is applied to oe pin, all the ledn outputs are enabled as defined by the chase register. ? when a high level is applied to oe pin, all the ledn outputs are high-impedance. the oe pin can be used as a synchronization signal to switch on/off several pcu9656 devices at the same time. this requires an exte rnal clock reference that provides blinking period and the duty cycle. the oe pin can also be used as an external dimming control signal. the frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the leds. remark: do not use oe as an external blinking control signal when internal global blinking is selected (dmblnk = 1, mode2 register) since it will result in an undefined blinking pattern. do not use oe as an external dimming control signal when internal global dimming is selected (dmblnk = 0, mode2 register) since it will result in an undefined dimming pattern. remark: during power-down, slow decay of volt age supplies may keep leds illuminated. consider disabling ledn outputs using high level applied to oe pin. 7.5 power-on reset when power is applied to v dd , an internal power-on reset holds the pcu9656 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pcu9656 registers and i 2 c-bus state machine are initializ ed to their default states (all zeroes) causing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device. 7.6 software reset the software reset call (swrst call) allows all the devices in the ufm i 2 c-bus to be reset to the power-up state value through a specific formatted i 2 c-bus command. the swrst call function is defined as the following: 1. a start command is sent by the ufm i 2 c-bus master. 2. the reserved swrst ufm i 2 c-bus address ?0000 011? with the r/w bit set to ?0? (write) is sent by the i 2 c-bus master. 3. since pcu9656 is a ufm i 2 c-bus device, no acknowledge is returned to the i 2 c-bus master. 4. once the swrst call address has been sent, the master sends 2 bytes with two specific values (swrst data byte 1 and byte 2): byte 1 = a5h, byte 2 = 5ah. if more than 2 bytes of data are sent , they will be igno red by the pcu9656.
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 24 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 5. once the right 2 bytes (swrst data byte 1 and byte 2 only) have been sent, the master sends a stop command to end the swrst call: the pcu9656 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (t buf ). remark: the reset stage is also the standby stat e with the internal oscillator turned off. it takes 500 ? s for the oscillator to be up and running on ce the sleep bit has been set to a logic 1. pwm registers should not be accessed within the 500 ? s window. 7.7 individual brightness contro l with group dimming/blinking a 97 khz typical frequency signal with programmabl e duty cycle (8 bits, 256 steps) is used to control individually the brightness for each led. on top of this signal, one of the following si gnals can be superimposed (this signal can be applied to the 24 ledn outputs): ? a lower 190 hz typical frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control. ? a programmable frequency signal from 24 hz to 1 10.73 hz (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. minimum pulse width for ledn brightness control is 40 ns. minimum pulse width for group dimming is 20.48 ? s. when m = 1 (grppwm register value), the resulting ledn br ightness control + group dimming signal will have 2 pulses of the led brightness control signal (pulse width = n ? 40 ns, with ?n? defined in pwmx register). this resulting brightness + group dimming signal above shows a resulting control signal with m = 4 (8 pulses). fig 6. brightness + group dimming signals 123456789101112 507 508 509 510 511 512 1234567891011 brightness control signal (ledn) m 256 2 40 ns with m = (0 to 255) (grppwm register) n 40 ns with n = (0 to 255) (pwmx register) 256 40 ns = 10.24 s (97.6 khz) 12345678 12345678 group dimming signal resulting brightness + group dimming signal 256 2 256 40 ns = 5.24 ms (190.7 hz) 002aab417
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 25 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 8. characteristics of the pcu9656 ultra fast-mode i 2 c-bus the pcu9656 led controller uses the new ultra fast-mode (ufm) i 2 c-bus to communicate with the ufm i 2 c-bus capable host controller. it uses two lines for communication. they are a serial data line (usda) and a serial clock line (uscl). the ufm is a unidirectional bus that is capable of higher frequency (up to 5 mhz). the ufm i 2 c-bus slave devices operate in re ceive-only mode. that is, only i 2 c writes to pcu9656 are supported. 8.1 bit transfer one data bit is transferred during each cl ock pulse. the data on the usda line must remain stable during the high period of the cl ock pulse as changes in the data line at this time will be interpreted as control signals (see figure 7 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 8 ). fig 7. bit transfer 002aaf113 data line stable; data valid change of data allowed usda uscl fig 8. definition of start and stop conditions 002aaf114 usda uscl p stop condition s start condition
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 26 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 8.2 system configuration a device generating a message is a ?transmitter ?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 9 ). 8.3 data transfer the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one bit that is always set to 1. the master gene rates an extra related clock pulse. fig 9. system configuration 002aaf100 slave ufm receiver usda uscl master ufm transmitter slave ufm receiver slave ufm receiver fig 10. data transfer 002aaf101 s start condition 9 8 2 1 usda data output by master ufm transmitter uscl clock from master
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 27 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 9. bus transactions (1) see table 4 for register definition. fig 11. write to a specific register a5 a4 a3 a2 a1 a0 0 1 s 0 slave address start condition w this bit always = 1 002aag251 data for register d[7:0] 0 d5 d4 d3 d2 d1 d0 aif control register (1) auto-increment flag 1 this bit always = 1 1 this bit always = 1 p stop condition register address (1) (1) ai1, ai0 = 00b. see ta b l e 3 for auto-increment options. remark: care should be taken to load the appropriate value here in the ai1 and ai0 bits of the mode1 register for programming the part with the required auto-increment options. fig 12. write to all registers using the auto-increment feature a5 a4 a3 a2 a1 a0 0 1 s 0 slave address start condition w this bit always = 1 002aag252 mode1 register (1) d[7:0] 0 0 0 0 0 0 0 1 control register auto-increment on 1 this bit always = 1 1 this bit always = 1 p stop condition (cont.) (cont.) mode1 register selection mode2 register d[7:0] 1 this bit always = 1 subadr3 register d[7:0] 1 this bit always = 1 allcalladr register d[7:0] 1 this bit always = 1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 28 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver this example assumes that aif + ai[1:0] = 101b. fig 13. multiple writes to indivi dual brightness registers only using the auto-increment feature a5 a4 a3 a2 a1 a0 0 1 s 0 slave address start condition w this bit always = 1 002aag253 pwm0 register data 0 0 0 0 0 1 0 1 control register auto-increment on 1 this bit always = 1 1 this bit always = 1 p stop condition (cont.) (cont.) pwm0 register selection pwm1 register data 1 this bit always = 1 pwm22 register data 1 this bit always = 1 pwm23 register data 1 this bit always = 1 pwm0 register data 1 this bit always = 1 register rollover pwm22 register data 1 this bit always = 1 pwm23 register data 1 this bit always = 1
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 29 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver (1) in this example, several pcu9656s are used and the same sequence (a) (above) is sent to each of them. (2) allcall bit in mode1 register is pr eviously set to 1 for this example. (3) och bit in mode2 register is prev iously set to 1 for this example. fig 14. led all call ufm i 2 c-bus address programming and led all call sequence example a5 a4 a3 a2 a1 a0 0 1 s 0 slave address (1) start condition w this bit always = 1 002aag254 0 1 0 0 1 1 0 1 control register auto-increment on 1 this bit always = 1 allcalladr register selection 0 1 0 1 0 1 0 1 new led all call ufm i 2 c address (2) p stop condition 1 this bit always = 1 0 1 0 1 0 1 0 1 s 1 led all call ufm i 2 c address start condition w this bit always = 1 0 0 1 1 1 0 1 1 control register 1 this bit always = 1 ledout0 register selection 1 0 1 0 1 0 1 0 ledout0 register (led fully on) p stop condition 1 this bit always = 1 led[3:0] are on at the ninth bit (3) sequence (a) sequence (b)
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 30 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 10. application design-in information (1) oe requires pull-up resistor if control signal from the master is open-drain. i 2 c-bus address = 0010 101x. remark: during power-down, slow decay of voltage supplies may keep leds illuminated. consi der disabling ledn outputs using high level applied to oe pin. fig 15. typical application pcu9656 led0 led1 usda uscl oe v dd = 2.5 v, 3.3 v or 5.0 v ufm i 2 c-bus/ smbus master usda uscl oe led2 led3 a0 a1 a2 v dd a3 a4 a5 v ss 10 k (1) led8 led9 led10 led11 up to 40 v led light bar led12 led13 led14 led15 up to 40 v led light bar v ss up to 40 v led4 led5 led6 led7 up to 40 v led light bar up to 40 v led16 led17 led18 led19 led light bar led20 led21 led22 led23 up to 40 v led light bar 002aag255 up to 40 v
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 31 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 10.1 junction temperature calculation a device junction temperature can be calculated when the ambient temperature or the case temperature is known. when the ambient temperature is known, the junction temperature is calculated using equation 4 and the ambient temperature, junction to ambient thermal resistance and power dissipation. (4) where: t j = junction temperature t amb = ambient temperature r th(j-a) = junction to ambient thermal resistance p tot = (device) total power dissipation when the case temperature is known, the junction temperature is calculated using equation 5 and the case temperature, junction to case thermal resistance and power dissipation. (5) where: t j = junction temperature t case = case temperature r th(j-c) = junction to case thermal resistance p tot = (device) total power dissipation here are two examples regarding how to calc ulate the junction temperature using junction to case and junction to ambient thermal resistance. in the first example ( section 10.1.1 ), given the operating condition and the junction to ambient thermal resistance, the junction temperature of PCU9656B, in the lqfp48 packa ge, is calculated for a system operating condition in 50 ? c 1 ambient temperature. in the second example ( section 10.1.2 ), based on a specific customer application requirem ent where only the case temperature is known, applying the junction to case thermal resistance equation, the junction temperature of the PCU9656B, in t he lqfp48 package, is calculated. 1. 50 ? c is a typical temperature inside an enclosed system. the designers should feel free, as needed, to perform their own calculation using the examples. t j t amb r th j - a ?? p tot ? += t j t case r th j - c ?? p tot ? +=
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 32 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 10.1.1 example 1: t j calculation when t amb is known (PCU9656B, lqfp48) r th(j-a) = 63 ? c/w t amb = 50 ? c ledn output low voltage (led v ol ) = 0.5 v ledn output current per channel = 80 ma number of outputs = 24 i dd(max) = 18 ma v dd(max) = 5.5 v 1. find p tot (device total power dissipation): ? output total power = 80 ma ? 24 ? 0.5 v = 960 mw ? chip core power consumption = 18 ma ? 5.5 v = 99 mw p tot = (960 + 99 + 10 + 10) mw = 1059 mw 2. find t j (junction temperature): t j = (t amb +r th(j-a) ? p tot ) = (50 ? c + 63 ? c/w ? 1059 mw) = 116.7 ? c 10.1.2 example 2: t j calculation where only t case is known this example uses a customer?s specific ap plication of the PCU9656B, 24-channel led controller in the lqfp48 package, where only the case temperature (t case ) is known. t j = t case + r th(j-c) ? p tot , where: r th(j-c) = 18 ? c/w t case (measured) = 94.6 ? c v ol of led ~ 0.5 v i dd(max) = 18 ma v dd(max) = 5.5 v ledn output voltage low = 0.5 v ledn output current: 60 ma on 1 port = (60 ma ? 1) 50 ma on 6 ports = (50 ma ? 6) 40 ma on 2 ports = (40 ma ? 2) 20 ma on 12 ports = (20 ma ? 12) 1 ma on 3 ports = (1 ma ? 3)
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 33 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 1. find p tot (device total power dissipation) ? output current (60 ma ? 1 port); output power (60 ma ? 1 ? 0.5 v) = 30 mw ? output current (50 ma ? 6 ports); output power (50 ma ? 6 ? 0.5 v) = 150 mw ? output current (40 ma ? 2 ports); output power (40 ma ? 2 ? 0.5 v) = 40 mw ? output current (20 ma ? 12 ports); output power (20 ma ? 12 ? 0.5v) = 120mw ? output current (1 ma ? 3 ports); output power (1 ma ? 3 ? 0.5v) = 1.5mw output total power = 341.5 mw ? chip core power consumption = 18 ma ? 5.5 v = 99 mw p tot (device total power dissipation) = 440.5 mw 2. find t j (junction temperature): t j = t case + r th(j-a) ? p tot = 94.6 ? c + 18 ? c/w ? 440.5 mw = 102.5 ? c 11. limiting values [1] each bit must be limited to a maximum of 100 ma and the total package limited to 2400 ma due to internal busing limits. [2] refer to section 10.1 for calculation. table 15. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.0 v v i/o voltage on an input/output pin v ss ? 0.5 5.5 v v drv(led) led driver voltage v ss ? 0.5 40 v i o(ledn) output current on pin ledn - 100 ma i ol(tot) total low-level output current led driver outputs; v ol =0.5v [1] 2400 - ma i ss ground supply current per v ss pin - 800 ma p tot total power dissipation t amb =25 ? c-1 . 8w t amb =85 ?c - 0.72 w p/ch power dissipation per channel t amb =25 ? c-1 0 0m w t amb =85 ? c-4 5m w t j junction temperature [2] - +125 ?c t stg storage temperature ? 65 +150 ?c t amb ambient temperature operating ? 40 +85 ?c
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 34 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver [1] this value signifies package?s abi lity to handle more than 100 ma per output driver. the device?s maximum current rating per output is 100 ma. 12. thermal characteristics [1] calculated in accordance with jesd 51-7. table 16. lqfp48 power dissipation and output current capability measurement lqfp48 t amb = 25 ? c maximum power dissipation (chip + output drivers) 1590 mw maximum power dissipation (output drivers only) 1460 mw maximum drive current per channel [1] t amb = 60 ? c maximum power dissipation (chip + output drivers) 1030 mw maximum power dissipation (output drivers only) 901 mw maximum drive current per channel t amb = 80 ? c maximum power dissipation (chip + output drivers) 714 mw maximum power dissipation (output drivers only) 585 mw maximum drive current per channel 1460 mw 24 - bit 0.5 v ? ---------------------------------- - ? 121.7 ma = 901 mw 24 - bit 0.5 v ? ---------------------------------- - ? 75.1 ma = 585 mw 24 - bit 0.5 v ? ---------------------------------- - ? 48.8 ma = table 17. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient lqfp48 [1] 63 ? c/w r th(j-c) thermal resistance from junction to case lqfp48 [1] 18 ? c/w
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 35 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 13. static characteristics [1] v dd must be lowered to 0.2 v in order to reset part. [2] each bit must be limited to a maximum of 100 ma and the to tal package limited to 2400 ma due to internal busing limits. table 18. static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = ? 40 ? cto+85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 5.5 v i dd supply current on pin v dd ; operating mode; no load; f uscl =5mhz v dd = 2.7 v - 0.5 5.5 ma v dd =3.6v - 1.5 8 ma v dd =5.5v - 17 25 ma i stb standby current on pin v dd ; no load; f uscl =0hz; i/o = inputs; v i =v dd v dd =2.7v - 0.5 5 ? a v dd =3.6v - 1.0 10 ? a v dd =5.5v - 6 15 ? a v por power-on reset voltage no load; v i =v dd or v ss [1] -1.702.0v ufm i 2 c-bus inputs uscl and usda v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i l leakage current v i =v dd or v ss ? 1- +1 ? a c i input capacitance v i =v ss -6 10 pf led driver outputs (led[23:0]) v drv(led) led driver voltage 0 - 40 v i ol low-level output current v ol =0.5v; v dd ? 4.5 v [2] 100 - - ma i loh high-level output leakage current v drv(led) =5v - - ? 1 ? a v drv(led) =40v - ? 115 ? a r on on-state resistance v ol =0.5v; v dd =2.3v - 2 5 ? c o output capacitance - 15 40 pf oe input v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1- +1 ? a c i input capacitance - 3.7 5 pf address inputs (a[5:0]) v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1- +1 ? a c i input capacitance - 3.7 5 pf
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 36 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 14. dynamic characteristics [1] for led off to fully on, led fully on to of f, or led individual brightness control to off. [2] for led off to individual brightness cont rol or changes in the individual brightnes s control value, there is a synchronizati on that may take up to 15 ? s for the change to take effect. table 19. dynamic characteristics symbol parameter conditions min typ max unit f uscl uscl clock frequency - - 5 mhz t buf bus free time between a stop and start condition 0.08 - - ? s t hd;sta hold time (repeated) start condition 0.05 - - ? s t su;sta set-up time for a repeated start condition 0.05 - - ? s t su;sto set-up time for stop condition 0.05 - - ? s t hd;dat data hold time 10 - - ns t su;dat data set-up time 30 - - ns t low low period of the uscl clock 0.05 - - ? s t high high period of the uscl clock 0.05 - - ? s t f fall time of both usda and uscl signals - - 50 ns t r rise time of both usda and uscl signals - - 50 ns t sp pulse width of spikes that must be suppressed by the input filter --10ns output propagation delay t plh low to high propagation delay oe to ledn; mode2[1:0] = 01 - - 150 ns t phl high to low propagation delay oe to ledn; mode2[1:0] = 01 - - 150 ns output port timing [1] [2] t d(uscl-q) delay time from uscl to data output uscl to ledn; mode2[3] = 1; ledoutx = 01; outputs change on ninth clock cycle (uscl) - - 450 ns t d(usda-q) delay time from usda to data output usda to ledn; mode2[3] = 0; ledoutx = 01; outputs change on stop condition - - 450 ns
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 37 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 15. test information rise and fall times refer to v il and v ih . fig 16. ufm i 2 c-bus timing and output timing diagram uscl usda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high 002aag616 t su;sto protocol start condition (s) bit 7 msb bit 6 bit 1 (d1) bit 0 (d0) 1 / f uscl t r (always set to 1 by master) stop condition (p) 9th clock 0.3 v dd 0.7 v dd 0.3 v dd 0.7 v dd output data led[0:23] t d(uscl-q) t d(usda-q) output data led[0:23] fig 17. output propagation delay 002aag604 oe t plh output data t phl r l = load resistor for ledn. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 18. test circuitry for switching times pulse generator v o c l 50 pf r l 500 002aab177 r t v i v dd v dd d.u.t.
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 38 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 16. package outline fig 19. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 39 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 17. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are:
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 40 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 18.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 20 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 0 and 21 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 20 . table 20. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 21. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 41 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 19. abbreviations msl: moisture sensitivity level fig 20. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 22. abbreviations acronym description ack acknowledge cdm charged device model esd electrostatic discharge fet field-effect transistor hbm human body model i 2 c-bus inter-integrated circuit bus led light emitting diode lsb least significant bit msb most significant bit pcb printed-circuit board pwm pulse width modulation rgb red/green/blue rgba red/green/blue/amber smbus system management bus ufm ultra-fast mode (i 2 c-bus)
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 42 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 20. revision history table 23. revision history document id release date data sheet status change notice supersedes pcu9656 v.1 20111208 product data sheet - -
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 43 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 21.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 21.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcu9656 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 8 december 2011 44 of 45 nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 21.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcu9656 24-bit ufm 5 mhz i 2 c-bus 100 ma 40 v led driver ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 december 2011 document identifier: pcu9656 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 device addresses . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 regular ufm i 2 c-bus slave address . . . . . . . . 6 7.1.2 led all call ufm i 2 c-bus address. . . . . . . . . . 7 7.1.3 led sub call ufm i 2 c-bus addresses. . . . . . . 7 7.1.4 software reset ufm i 2 c-bus address . . . . . . . 7 7.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 register definitions . . . . . . . . . . . . . . . . . . . . . . 9 7.3.1 mode register 1, mode1 . . . . . . . . . . . . . . . . 11 7.3.2 mode register 2, mode2 . . . . . . . . . . . . . . . . 11 7.3.3 pwm0 to pwm23, individual brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.3.4 grppwm, group duty cycle control . . . . . . . . 13 7.3.5 grpfreq, group frequency . . . . . . . . . . . . . 13 7.3.6 chase control . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3.7 ledout0 to ledout 5, led driver output state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3.8 subadr1 to subadr3, ufm i 2 c-bus subaddress 1 to 3 . . . . . . . . . . . . . . . . . . . . . . 22 7.3.9 allcalladr, led all call ufm i 2 c-bus address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 active low output enable input . . . . . . . . . . . 23 7.5 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 software reset. . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7 individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 24 8 characteristics of the pcu9656 ultra fast-mode i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . 25 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1.1 start and stop conditions . . . . . . . . . . . . . 25 8.2 system configuration . . . . . . . . . . . . . . . . . . . 26 8.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 27 10 application design-in information . . . . . . . . . 30 10.1 junction temperature calculation . . . . . . . . . . 31 10.1.1 example 1: t j calculation when t amb is known (PCU9656B, lqfp48) . . . . . . . . . . . . 32 10.1.2 example 2: t j calculation where only t case is known . . . . . . . . . . . . . . . . . . . . . . . . 32 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33 12 thermal characteristics . . . . . . . . . . . . . . . . . 34 13 static characteristics . . . . . . . . . . . . . . . . . . . 35 14 dynamic characteristics. . . . . . . . . . . . . . . . . 36 15 test information . . . . . . . . . . . . . . . . . . . . . . . 37 16 package outline. . . . . . . . . . . . . . . . . . . . . . . . 38 17 handling information . . . . . . . . . . . . . . . . . . . 39 18 soldering of smd packages . . . . . . . . . . . . . . 39 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 39 18.2 wave and reflow soldering. . . . . . . . . . . . . . . 39 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 39 18.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 40 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 42 21 legal information . . . . . . . . . . . . . . . . . . . . . . 43 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 21.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44 22 contact information . . . . . . . . . . . . . . . . . . . . 44 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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